Signal Integrity Power Integrity Engineer

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THE ROLE:

AMD is seeking an experienced Signal Integrity & Power Integrity design engineer for the development and silicon verification of high-performance FPGA configuration in the company's next generation products. Successful candidates will be responsible for design and development of assigned system platform to ensure the design meets all defined quality metrics. You will also provide back-end design development guidelines for system IO development, system SIPI modeling development support. The other responsibilities will include system validation & characterization of FPGA platform. As a member of the System Integration Group and SI PI team, you will have wide array of opportunities to work with different design Center of Excellence teams on design flow, VIVADO flow, and system SIPI verification. Close interaction with both the PHY design team, physical board design team and system memory controller team is essential

THE PERSON:

The type of person who will be successful in this role is highly inquisitive, a team player who communicates proactively. You will exhibit excellent written and verbal communication skills and you will be highly analytical.

Applicants should possess a MS or PhD in EE or equivalent field with applicable work experience in the several of the following tools. The position requires comprehensive knowledge of Signal Integrity & Power Integrity design methodology. Prior work experience in FPGA design and system memory IO is plus.

KEY RESPONSIBILITIES:

• Implement system SIPI system design model for high-speed channel analysis.
• Drive and Develop SIPI system analysis plan.
• Mentor Junior Engineer to develop SIPI analysis models.
• Run SIPI checks using signal integrity tools such as HFSS, ADS, Power SI and or SI Wave.
• Support routing guideline development.
• Support system SIPI validation and characterization.
• Support System Debug & testing on bench or ATE tester

PREFERRED EXPERIENCE:

• Hands on experience in SIPI analysis for PCB channel & die package, which includes but not limited to layout extraction, electromagnetic and HSPICE simulation to meet silicon design spec and analysis.
• Channel (SI) analysis for I/O chancel & power domain. Eye diagram and jitter analysis via Chip-package-board co-simulation.
  • Signal trace length matching and impact to timing.
  • Optimal layer stackup & power plane assignment to minimize voltage & signal noise.
• Crosstalk analysis and reduction.
• Full-wave simulation and model extraction for signal integrity and power integrity analysis
  • Possess excellent verbal and written communication skills

ACADEMIC CREDENTIALS:

• Master or PhD Degree in Electrical Engineering, or related equivalent

LOCATION:

• San Jose, California

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At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD's Employee Stock Purchase Plan. You'll also be eligible for competitive benefits described in more detail .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.