What are the responsibilities and job description for the RF Layout Engineer position at Galaxy Infotech Inc.?
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Apple
6 months
Location (onsite) – San Diego (preferred), Cupertino (will work), Irvine (possible)
No H1B
Skills
RF Layout
Cadence tools
FINFET
7nm
Key Qualifications
Experience in custom RF/analog layout with extensive knowledge of deep sub-micron CMOS (40nm, 28nm, 7nm FinFET, etc.)
Knowledgable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
Solid understanding of RC delay, electromigration, and coupling
Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
Knowledge of CADENCE layout tools
Excellent communication skills and able to work with cross-functional teams
You would also have the following, if you're more experienced:
Capability to lead other layout engineers for top-level integration
Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
Scripting skills in PERL or SKILL are a plus, but not required
Description
As a RF layout engineer, you will be responsible for
Apple
6 months
Location (onsite) – San Diego (preferred), Cupertino (will work), Irvine (possible)
No H1B
Skills
RF Layout
Cadence tools
FINFET
7nm
Key Qualifications
Experience in custom RF/analog layout with extensive knowledge of deep sub-micron CMOS (40nm, 28nm, 7nm FinFET, etc.)
Knowledgable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
Solid understanding of RC delay, electromigration, and coupling
Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
Knowledge of CADENCE layout tools
Excellent communication skills and able to work with cross-functional teams
You would also have the following, if you're more experienced:
Capability to lead other layout engineers for top-level integration
Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
Scripting skills in PERL or SKILL are a plus, but not required
Description
As a RF layout engineer, you will be responsible for
- Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
- Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking
- Co-work with designers on block level and top-level floorplanning
- Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling
- Top-level layout integration and verification, schedule management