CADEDA Silicon DesignVerification Infrastructure engineer

Job Description

Role : Verification Infrastructure Engineer

Location : San Francisco, CA / Seattle, WA / Santa Clara, CA

Interview : Phone / Skype

Job Type : Contract

CAD / EDA – Silicon Design / Verification Infrastructure

Minimum Qualifications :

Minimum 5 years of experience in EDA / CAD SoC / IP design and / or verification infrastructure development

Proficiency in modern Python (Python 3.x) - intermediate or above - demonstrated by work experience

knowledge of AISC / SoC flow, System Verilog / UVM

Experience in development in Linux based environments (Shell scripting, Makefile, etc.)

• Work on subsystems with multiple processors (ARM / RISC) and NOC, focusing on integration testing, and top-level functionalities.
• Utilize your experience with UVM-based SoC verification.
• Apply your working knowledge of C to understand existing code, write basic tests, compile, and create hex code for processor tests.
• Engage in design verification involving concurrency and simultaneous memory access.
• Define and implement SoC verification plans and build verification test benches for sub-system / SoC level verification.
• Develop functional tests based on the verification test plan.
• Drive design verification to closure using defined metrics for test plans, functional, and code coverage.
• Debug, root-cause, and resolve functional failures in the design in collaboration with the Design team.
• Collaborate with cross-functional teams (Design, Model, Emulation, and Silicon validation) to ensure the highest design quality.
• Develop and drive continuous improvements in design verification using the latest methodologies, tools, and technologies.

Qualifications :

Additional Information

All your information will be kept confidential according to EEO guidelines.