What are the responsibilities and job description for the Design Verification Engineer at Santa Clara, CA (Onsite) position at Mapout Digital Solutions Inc?
Job Role: Design Verification Engineer
Work location: Santa Clara, CA (Onsite)
Key Responsabilities
Work location: Santa Clara, CA (Onsite)
Key Responsabilities
- Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
- Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
- Synopsys/Cadence EDA Verifications tools (Preference: 5)
- SystemVerilog/UVM (Preference: 5)
