What are the responsibilities and job description for the Principal Design Verification Engineer position at Marvell Technology?
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
PHY verification group works closely with Analog and Digital design teams and Systems/DSP teams to incorporate and build models for mixed signal designs and validate the design against the system architecture and requirements and sets up the API building infrastructure and guidelines for the software/driver team.
What You Can Expect
137,510 - 206,000, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation And Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
PHY verification group works closely with Analog and Digital design teams and Systems/DSP teams to incorporate and build models for mixed signal designs and validate the design against the system architecture and requirements and sets up the API building infrastructure and guidelines for the software/driver team.
What You Can Expect
- Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers.
- Work closely with architects/RTL engineers to bring-up a new architecture/micro-architecture on the verification environment
- Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete.
- Develop tests and tune the environment to achieve coverage goals.
- Own and debug failures in simulation to root cause problems
- Architecting, developing, and maintaining tools to streamline the design of state-of-the-art multicore SoCs.
- Analysis/closure of code and functional coverage.
- Experience in verification and simulation of Mixed signal designs which include but not limited to PLL and High Speed Serdes, 802.3 and related standards
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 12 plus years of related professional experience.
- Or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
- Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology)
- Good scripting skills in languages such as Perl, Tcl, or Python.
- Experience in developing testbench environments for networking protocols or microprocessors
- Experience in Physical layer networking protocols is a plus
- Good verbal and written communication skills in English
137,510 - 206,000, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation And Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
