What are the responsibilities and job description for the Senior Design Verification Engineer position at Mirafra Technologies?
- Contribute to verification methodology with a scalable solution across blocks, subsystems, fullchip and system-level validation
- Own portions of verification execution at subsystem and chip-level and create testbenches, tests and related artifacts to achieve structural and functional coverage closure
- Plan and drive intermediate and sign-off reviews on verification test plans, execution progress and verification closure towards various silicon milestones including design freeze and tapeout
Requirements:
- Concept-to-silicon experience in driving verification from an architecture and/or design specification to production silicon
- Experience with SystemVerilog, Python, C/C , Bluespec and similar scripting and programming languages for verification and silicon modeling
- Production experience with advanced verification methodologies such as UVM, assertion-based verification (ABV); experience and comfort with formal and simulated verification are required
- Production experience with creating portable tests and drivers for verification that apply to silicon validation and post-silicon debug
- Strong understanding of silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities
- Familiarity with emulation and prototyping platforms and methodologies is a plus
- Hands-on experience with participation in silicon debug and bring-up is a plus
Preferred Skills:
Min 7 direct experience in any of -
- Ethernet mac/pcs VIP integration tests preferrably network on chip testing.
- Pcie subsystem VIP integration tests preferrably embedded risc-v type uP integration tests.
- HBM subsystem tests.
Emulation infrastructure setup (palladium/protium or zebu).