Analog Layout Engineer

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Analog Layout Engineer at Yochana

Fremont, CA | Full Time
$123k-146k (estimate)
7 Months Ago

Analog Layout Engineer at Glint Tech Solutions

Fremont, CA | Full Time
$123k-146k (estimate)
7 Months Ago

Analog Layout Engineer at PER International

Fremont, CA | Full Time
$123k-146k (estimate)
7 Months Ago

Analog Layout Engineer at PER International

San Jose, CA | Full Time
$123k-146k (estimate)
7 Months Ago

Analog Layout Engineer at Apple

Waltham, MA | Full Time
$110k-131k (estimate)
7 Months Ago

Analog Layout Engineer at TetraMem - Accelerate The World

Fremont, CA | Full Time
$123k-146k (estimate)
8 Months Ago

Analog Layout Engineer at TetraMem - Accelerate The World

Fremont, CA | Full Time
$123k-146k (estimate)
8 Months Ago

Analog Layout Engineer at TetraMem - Accelerate The World

Fremont, CA | Full Time
$123k-146k (estimate)
8 Months Ago

Analog Layout Engineer at BroadAxis

Santa Clara, CA | Full Time
$123k-146k (estimate)
8 Months Ago

Analog Layout Engineer at Apple

Beaverton, OR | Full Time
$98k-116k (estimate)
9 Months Ago
Summary. Posted. Dec 11, 2024. Weekly Hours. 40. Role Number. 200582909. Apple Silicon Engineering Group (SEG) is seeking experienced Analog Layout Engineers to work on the next generation of Apple's systems-on-chip (SOCs). These SOCs, with multi-billion transistors, serve as the core of iPhones and iPads. We focus on Analog/Mixed-Signal (AMS) circuits, including SerDes for data communication, PLLs for clock generation, and sensors for measuring ...

Analog Layout Engineer at Glow Networks

Santa Clara, CA | Full Time
$89k-111k (estimate)
11 Months Ago
Position Overview. We are seeking a highly skilled Senior Layout Designer to lead the layout design of high-performance analog cores, including analog-to-digital converters, digital-to-analog converters, PLLs, and transceivers. This role requires expertise in cutting-edge, high-speed CMOS integrated circuits across various advanced foundry process nodes (3nm, 5nm, 7nm, 16nm). Key Responsibilities. . Lead the IC layout of high-performance, high-sp...
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