What are the responsibilities and job description for the FPGA/ASIC Verification Engineer position at PTR Global?
Job Details
HYBRID IN GOLETA, CA
Role Title: FPGA/ASIC Verification Engineer
Duration: 6 months [possible extension to 9 months total]
Work Location: Hybrid, Goleta, CA
Work Schedule: Normal PST business hours, Monday - Friday
Project Overview:
The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to driven the internal components and send data.
Overall Responsibilities:
As a FPGA/ASIC Design Verification Engineer, you will own functional verification for a custom controller. You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the verification effort.
In this role, you will develop test plans for functional units and subsystems. You will analyze coverage from various dimensions and develop monitors and checkers for better quality assurance. In the final stages, you will also run GLS related simulations.
Top 3 Daily Responsibilities:
Responsibilities include the following:
Mandatory Skills/Qualifications: (All skills, both technical and soft, required to be successful in the role)
? Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related
field, or equivalent practical experience.
? 8 years of experience with verification methodologies and languages such as UVM and
SystemVerilog.
? Experience developing and maintaining verification testbenches, test cases, and test
environments.
? Experience in all aspects of verification life cycle, specifically, SDF and GLS simulations
? Experience in ethernet and SPI required
Non-Essential Skills/Qualifications: (Skills that would be nice to have but are not essential in the role)
? Master's degree in Electrical Engineering, Computer Science, or related field.
? UVM/System verilog experience 5 years (10 years preferred
? High proficiency in python
? Knowledge of general purpose operating systems such as Linux and Android.
? Experience in assertions and formal verification preferred
? Experience in ethernet, SPI, AXI, JTAG preferred
? Experience in analog and real number modeling preferred
Pay Range: $90-110/ hr
The specific compensation for this position will be determined by a number of factors, including the scope, complexity and location of the role as well as the cost of labor in the market; the skills, education, training, credentials and experience of the candidate; and other conditions of employment. Our fulltime consultants have access to benefits including medical, dental, vision and 401K contributions as well as any other PTO, sick leave, and other benefits mandated by appliable state or localities where you reside or work.
#LI-AP3
Role Title: FPGA/ASIC Verification Engineer
Duration: 6 months [possible extension to 9 months total]
Work Location: Hybrid, Goleta, CA
Work Schedule: Normal PST business hours, Monday - Friday
Project Overview:
The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to driven the internal components and send data.
Overall Responsibilities:
As a FPGA/ASIC Design Verification Engineer, you will own functional verification for a custom controller. You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the verification effort.
In this role, you will develop test plans for functional units and subsystems. You will analyze coverage from various dimensions and develop monitors and checkers for better quality assurance. In the final stages, you will also run GLS related simulations.
Top 3 Daily Responsibilities:
Responsibilities include the following:
- UVM/python test development for driving VIPs and other stimulus drivers
- Generation of test components such as monitors, scoreboards and python models
- Coverage closure and GLS bringup and testing
Mandatory Skills/Qualifications: (All skills, both technical and soft, required to be successful in the role)
? Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related
field, or equivalent practical experience.
? 8 years of experience with verification methodologies and languages such as UVM and
SystemVerilog.
? Experience developing and maintaining verification testbenches, test cases, and test
environments.
? Experience in all aspects of verification life cycle, specifically, SDF and GLS simulations
? Experience in ethernet and SPI required
Non-Essential Skills/Qualifications: (Skills that would be nice to have but are not essential in the role)
? Master's degree in Electrical Engineering, Computer Science, or related field.
? UVM/System verilog experience 5 years (10 years preferred
? High proficiency in python
? Knowledge of general purpose operating systems such as Linux and Android.
? Experience in assertions and formal verification preferred
? Experience in ethernet, SPI, AXI, JTAG preferred
? Experience in analog and real number modeling preferred
Pay Range: $90-110/ hr
The specific compensation for this position will be determined by a number of factors, including the scope, complexity and location of the role as well as the cost of labor in the market; the skills, education, training, credentials and experience of the candidate; and other conditions of employment. Our fulltime consultants have access to benefits including medical, dental, vision and 401K contributions as well as any other PTO, sick leave, and other benefits mandated by appliable state or localities where you reside or work.
#LI-AP3
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Salary : $90 - $110
