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DFT RTL Engineer

Triple Crown
Santa Clara, CA Contractor
POSTED ON 8/5/2025 CLOSED ON 9/3/2025

What are the responsibilities and job description for the DFT RTL Engineer position at Triple Crown?

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.


Contract Position


Location: Santa Clara, CA - will see remote candidates

Duration: 18 Months


We are seeking a highly skilled DFT RTL Engineer to join our SoC design team. This role is focused on Design-for-Test (DFT) features at the RTL level. The ideal candidate will have hands-on experience in scan architecture, Tessent flow setup, and DFX logic design, with solid RTL coding skills and simulation expertise. This is a DFT RTL role – not suited for general RTL designers or DFT ATPG engineers.


  • Develop and implement DFX RTL logic to support SoC Design-for-Test features.
  • Set up and optimize Mentor Tessent flow for scan insertion and DFT integration.
  • Define and implement scan requirements and scan architecture at the RTL level.
  • Design and code custom DFT features using Verilog RTL; SystemVerilog experience is a plus.
  • Perform RTL linting and CDC (Clock Domain Crossing) analysis to ensure design robustness.
  • Simulate and debug DFT logic using VCS and Verdi environments.
  • Collaborate with physical design and verification teams to ensure testability and proper integration.
  • Understand and work with design constraints (SDC) to guide DFT logic design.


Required Skills & Experience:


  • Strong background in DFT RTL development with experience integrating scan and test logic into SoC designs.
  • Proficiency in Mentor Tessent tools for scan planning and implementation.
  • Solid command of Verilog RTL coding; exposure to SystemVerilog is advantageous.
  • Experience running RTL lint and CDC checks.
  • Hands-on simulation experience using VCS and Verdi.
  • Understanding of SoC-level design constraints and timing requirements.
  • Proven ability to work cross-functionally with design, verification, and physical implementation teams.


Benefits:


  • Paid weekly!
  • Health, Dental and Vision Insurance
  • 401k

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